The present invention generally relates to the field of reset systems usable for resetting one or more microprocessors. More particularly, the present invention relates to a microprocessor reset system in which one microprocessor communicates with another via an information line and wherein each of the microprocessors is reset under certain condition.
Microprocessor reset systems exist wherein, in response to the occurrence of certain signal transitions, a reset pulse is provided to the microprocessor so as to interrupt its normal execution of commands and implement the execution of a different set of commands which form an interrupt subroutine. Typically, the reset pulse used to reset the microprocessor is provided in response to the occurrence of some event independent of and/or external to the microprocessor being reset. In some systems one microprocessor may transmit a signal which results in the resetting of another microprocessor. Some prior micropocessors are reset in response to the action of an independent timeout timer which provides a reset pulse at the reset terminal of the microprocessor.
In response to being reset, the microprocessor may provide, in some prior systems, a stream of information on an information output line separate from the reset terminal. Typically, the information line is not coupled to the reset terminal of the microprocessor, and this is to prevent the microprocessor from accidentally resetting itself in response to its output of information signals. This results in maintaining separate microprocessor information and reset lines. This can readily add to the cost of a microprocessor reset system when each of these lines has to be brought out external to the microprocessor package because access to the reset terminal is typically provided to an external apparatus and the microprocessor will typically communicate, via the information line, with an external apparatus which may comprise an additional microprocessor. When these separate external lines are connected from the microprocessor to external devices via plug and socket assemblies, the reliability of such a system is decreased since external plug and socket connectors for each of the separate information and reset lines must be provided, and a faulty connection between any of these connector lines results in a system failure.